This invention relates, in general, to a semiconductor component and, more particularly, to a metallization system in a semiconductor component
Semiconductor component manufacturers are constantly striving to increase the speed of the components they manufacture. Because a semiconductor component, such as a microprocessor, contains up to a billion transistors or devices, manufacturers have focused on decreasing the gate delays of the semiconductor devices to increase speed. As a result, manufacturers have decreased the gate delays such that speed is now primarily limited by the propagation delay of the metallization system used to interconnect the devices. Metallization systems are typically comprised of a plurality of metallic interconnect layers electrically isolated from each other by a dielectric material. A figure of merit describing the delay of the metallization system is the Resistor-Capacitance (RC) delay of the metallization system. The RC delay can be derived from the resistance of the metal layer and the associated capacitance between different layers of metal in the metallization system. More particularly, the RC delay is given by:
RC=(xcfx81*∈*l2/(tm*tdiel)
where:
xcfx81 is the resistivity of the metallic interconnect layer;
∈ is the dielectric constant or permittivity of the dielectric material;
l is the length of the metallic interconnect;
tm is the thickness of the metal; and
tox is the thickness of the dielectric material.
Thus, to decrease the RC delay, either the resistivity of the metallic interconnect layer, the dielectric constant of the dielectric material, the length of the metal interconnect, or a combination thereof need to be decreased. Alternatively, the RC delay can be decreased by increasing the thickness of the metallic interconnect and/or the thickness of the dielectric material. The most practical parameter to optimize is the dielectric constant of the dielectric material. To lower the dielectric constant, semiconductor manufacturers have been developing dielectric materials having a low dielectric constant, i.e., a low xcexa. However, the drawbacks of using low xcexa dielectric materials is that they are difficult to resolve into small contacts because of etch selectivity problems, they create particles when polished that contaminate the device, and these types of materials are very fragile.
Accordingly, what is needed is a structure and method for forming a metallization system that decreases the propagation delay by decreasing the dielectric constant of the dielectric material portion of the metallization system.
The present invention satisfies the foregoing need by providing a metallization system and a method for forming the metallization system, wherein the metallization system is suitable for use in a semiconductor component. In accordance with one embodiment, the metallization system comprises a substrate having a major surface and a metal-1 conductor disposed on a first portion of the major surface. A first dielectric material is disposed on a second portion of the major surface, which is adjacent to the first portion of the major surface. A second dielectric material is disposed on the conductor and a third portion of the major surface, which third portion is between the first and second portions. The dielectric constant of the first dielectric material is less than the dielectric constant of the second dielectric material. A conductive material extends through the second dielectric material and is electrically coupled to the conductor. A metal-2 conductor is disposed on the conductive material such that it is coupled to the metal-1 conductor by the conductive material extending through the second dielectric material.
In accordance with another embodiment, the present invention comprises a method for fabricating a metallization system. A substrate having a major surface is provided and a conductor is formed on a first portion of the major surface. A layer of low xcexa dielectric material is formed on the conductor and a second portion of the major surface. A via is formed through the first layer of dielectric material exposing a portion of the conductor and a portion of the major surface that is adjacent to the conductor. The via is filled with a dielectric material having a dielectric constant that is higher than the dielectric constant of the low xcexa dielectric material. The via is formed through the dielectric material having the higher dielectric constant and filled with an electrically conductive material. A conductor is formed on the electrically conductive material.
In accordance with yet another embodiment, the present invention comprises a method for manufacturing a metallization system suitable for use in a semiconductor component in which a substrate having a major surface is provided and a conductor is formed on a first portion of the major surface. A first layer of dielectric material is formed on the first conductor and the major surface. A portion of the dielectric material is removed and exposes a second portion of the major surface. The first layer of dielectric material is disposed on the conductor and a third portion of the major surface. The third portion is between the first and second portions. A second layer of dielectric material is formed on the second portion of the major surface. The first layer of dielectric material has a higher dielectric constant than the second layer of dielectric material. A via is formed through the second layer of dielectric material and filled with an electrically conductive material. A conductor is formed on the electrically conductive material.